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Cadence Design Systems Incisive PLD设计与仿真
  • Cadence Design Systems Incisive PLD设计与仿真

Cadence Design Systems Incisive PLD设计与仿真

更新时间：2023-02-21 21:32:26

为了满足当今手机、数码相机、电脑、自动系统及其他电子产品市场对于功能多样化的需求，生产商将数十亿计的晶体管集中于一个芯片上。这一集成同时伴随着向更小工艺技术的转变，芯片上的晶体管及其他物理装置比用来打印他们的光波还小。没有电子设计自动化

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Incisive Enterprise Simulator
Incisive Enterprise Simulator supports all IEEE-standard languages and methodologies as well as power formats and provides a comprehensive plan-to-closure methodology, improving productivity, project predictability, and product quality. Its unique capabilities support the intent, abstraction, and convergence needed to simplify and accelerate your workflow and help take the risk out of verification. The simulator acts as the:

  • Core engine for low-power verification working closely with Conformal® Low Power
  • Digital engine for mixed-signal verification working with Virtuoso simulators
  • Testbench engine for simulation acceleration with the Palladium platform
  • RTL engine working with transaction-level modeling (TLM) verification solutions

Incisive Functional Safety Simulator
Cadence Incisive Functional Safety Simulator is part of our functional safety solution that automates what can otherwise be a manual, time-consuming process of complying with functional safety requirements. The simulator provides seamless reuse of functional and mixed-signal verification environments.
Operating within the Incisive Enterprise Simulator compiled-code engine, Incisive Functional Safety Simulator accelerates the safety verification process by supporting seamless reuse of functional and mixed-signal verification environments. The simulator works with the new functional safety analysis capability in the Incisive vManager solution. Both are part of the Cadence System Development Suite.
Key Features

  • Support for multiple fault types, including single event upset (SEU), stuck-at-0/stuck-at-1, and single event transient
  • Reuse of the existing functional verification environment (with support for SystemVerilog, Universal Verification Methodology (UVM)

Incisive Specman Elite

  • Eliminates misrepresentations that lead to bug escapes
  • Provides rapid environment construction, scalability, and reuse
  • Automates test generation with up to 5X faster runtime

Incisive vManager Solution

  • Accelerates data collection, management, and analysis of functional verification
  • Automates verification signoff combined with executable verification plans
  • Improves design quality using forward-looking metrics and MDV methodology
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