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Cadence Design Systems Cadence Emulation Development Kit PLD设计与仿真
  • Cadence Design Systems Cadence Emulation Development Kit PLD设计与仿真

Cadence Design Systems Cadence Emulation Development Kit PLD设计与仿真

更新时间：2023-02-21 21:32:26

为了满足当今手机、数码相机、电脑、自动系统及其他电子产品市场对于功能多样化的需求，生产商将数十亿计的晶体管集中于一个芯片上。这一集成同时伴随着向更小工艺技术的转变，芯片上的晶体管及其他物理装置比用来打印他们的光波还小。没有电子设计自动化

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Cadence Emulation Development Kit
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Features

  • Remotely configure, use, and monitor using IP network
  • Supports remote protocol and traffic monitors
  • Supports Windows 7, Windows 10, and Linux OSs
  • Supports PCI Express Gen3 protocol interface with up to 16 lanes and L1 power management
  • Supports USB3.0 device interface with U0, U1, U2, and U3 power management

Benefits
Highest productivity with high fidelity

  • Offers higher verification performance than other verification methods without abstracting out critical portions of the design, while running in a real system environment that will be used in post-silicon validation
  • Full-speed performance and scalable with multi-interface designs or multiple interconnect technologies Offers rapid verification deployment
  • Provides a pre-validated emulation interface fully compatible with the Palladium series
  • Enables rapid creation of system-level environments using the same hardware and software that the real silicon will use

Enables reuse

  • Built around standards-compliant interfaces such as PCIe and USB, and can be reused for other projects
  • Improves productivity by getting the design running quickly without weeks or months of specialized test environment creation
  • Allows use of standard third-party protocol analysis tools, driver development suites, and traffic- generation utilities

Ensures quality

  • Tested and verified by Cadence against independent verification IP and other user designs
  • Cadence-provided solution lets you verify your design quickly and efficiently to ensure high product quality

Reduces system emulation bring up risk

  • Performs interface testing at the physical level
  • Runs full system enumeration connected to a real server chipset running a real OS with a full software stack

Does not abstract away low system- level connection issues that arise with real chipsets
Does not abstract away the real enumeration sequence of different OSs

  • Runs entire system-level real tests, just as the design silicon will have to do when it is deployed

Directed random testing is a vital andnecessary part of modern system verification, but it is not sufficient

  • Allows interaction with multiple system-level interconnects such as PCIe and USB, all in the same verification environment and without impacting performance
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